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| PRELIMINARY CY23EP05 2.5V or 3.3V,10- 220 MHz, Low Jitter, 5 Output Zero Delay Buffer Features * 10 MHz to 220 MHz maximum operating range * Zero input-output propagation delay, adjustable by loading on CLKOUT pin * Multiple low-skew outputs -- 30 ps typical output-output skew -- One input drives five outputs * 22 ps typical cycle-to-cycle jitter * 13 ps typical period jitter * Standard and High drive strength options * Available in space-saving 150-mil SOIC package * 3.3V or 2.5V operation * Industrial temperature available Functional Description The CY23EP05 is a 2.5V or 3.3V zero delay buffer designed to distribute low-jitter high-speed clocks and is available in a 8-pin SOIC package. It accepts one reference input, and drives out five low-skew clocks. The -1H version operates up to 220 (200) MHz frequencies at 3.3V (2.5V), and has a higher drive strength than the -1 devices. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The CY23EP05 PLL enters a power-down mode when there are no rising edges on the REF input (<~2 MHz). In this state, the outputs are three-stated and the PLL is turned off, resulting in less than 25 A of current draw. The CY23EP05 is available in different configurations, as shown in the Ordering Information table. The CY23EP05-1 is the base part. The CY23EP05-1H is the high-drive version of the -1, and its rise and fall times are much faster than the -1. These parts are not intended for 5V input-tolerant applications Block Diagram Pin Configuration Top View REF PLL CLKOUT CLK1 CLK2 CLK3 CLK4 REF CLK2 CLK1 GND 1 2 3 4 8 7 6 5 CLKOUT CLK4 V DD CLK3 Cypress Semiconductor Corporation Document #: 38-07759 Rev. ** * 3901 North First Street * San Jose, CA 95134 * 408-943-2600 Revised April 8, 2005 PRELIMINARY Pin Description Pin 1 2 3 4 5 6 7 8 REF[1] CLK2[2] CLK1[2] GND CLK3[2] VDD CLK4[2] CLKOUT[2,3] Signal Input reference frequency Buffered clock output Buffered clock output Ground Buffered clock output 3.3V or 2.5V supply Buffered clock output Buffered clock output, internal feedback on this pin Description CY23EP05 Zero Delay and Skew Control All outputs should be uniformly loaded to achieve Zero Delay between the input and output. Since the CLKOUT pin is the internal feedback to the PLL, its relative loading can adjust the input-output delay. The output driving the CLKOUT pin will be driving a total load of 5 pF plus any additional load externally connected to this pin. For applications requiring zero input-output delay, the total load on each output pin (including CLKOUT) must be the same. If input-output delay adjustments are required, the CLKOUT load may be changed to vary the delay between the REF input and remaining outputs. For zero output-output skew, be sure to load all outputs equally. For further information refer to the application note titled "CY2305 and CY2309 as PCI and SDRAM Buffers". Notes: 1. Weak pull-down. 2. Weak pull-down on all outputs. 3. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output. Document #: 38-07759 Rev. ** Page 2 of 11 PRELIMINARY Absolute Maximum Conditions Supply Voltage to Ground Potential ................. -0.5V to 4.6V DC Input Voltage ...................................... VSS - 0.5V to 4.6V CY23EP05 Storage Temperature .................................... -65C to 150C Junction Temperature .................................................. 150C Static Discharge Voltage (per MIL-STD-883, Method 3015..............................> 2000V Min. 3.0 2.3 0 -40 - - - - - - - - 1-1.5 0.8 29 41 37 41 0.01 131 81 50 Max. 3.6 2.7 70 85 30 30 22 22 15 15 15 5 Unit V V C C pF pF pF pF pF pF pF pF MHz MHz ms C/W C/W Operating Conditions Parameter VDD3.3 VDD2.5 TA CL [4] Description 3.3V Supply Voltage 2.5V Supply Voltage Operating Temperature (Ambient Temperature)--Commercial Operating Temperature (Ambient Temperature)--Industrial Load Capacitance, <100 MHz, 3.3V Load Capacitance, <100 MHz, 2.5V with High drive Load Capacitance, <133.3 MHz, 3.3V Load Capacitance, <133.3 MHz, 2.5V with High drive Load Capacitance, <133.3 MHz, 2.5V with Standard drive Load Capacitance, >133.3 MHz, 3.3V Load Capacitance, >133.3 MHz, 2.5V with High drive CIN BW ROUT Input Capacitance[5] Closed-loop bandwidth (typical), 3.3V Closed-loop bandwidth (typical), 2.5V Output Impedance (typical), 3.3V High drive Output Impedance (typical), 3.3V Standard drive Output Impedance (typical), 2.5V High drive Output Impedance (typical), 2.5V Standard drive tPU Theta Ja[6] Theta Jc[6] Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) Dissipation, Junction to Ambient, 8-pin SOIC Dissipation, Junction to Case, 8-pin SOIC 3.3V DC Electrical Specifications Parameter VDD VIL VIH IIL IIH VOL VOH IDD (PD mode) IDD Description Supply Voltage Input LOW Voltage Input HIGH Voltage Input Leakage Current Input HIGH Current Output LOW Voltage Output HIGH Voltage 0 < VIN < VIL VIN = VDD IOL = 8 mA (standard drive) IOL = 12 mA (High drive) IOH = -8 mA (standard drive) IOH = -12 mA (High drive) REF = 0 MHz (Industrial) Supply Current Unloaded outputs, 66-MHz REF Notes: 4. Applies to Test Circuit #1 5. Applies to both REF Clock and internal feedback path on CLKOUT 6. Theta Ja, EIA JEDEC 51 test board conditions, 2S2P; Theta Jc Mil-Spec 883E Method 1012.1 Test Conditions Min. 3.0 - 2.0 - - - - 2.4 2.4 - - - Max. 3.6 0.8 VDD + 0.3 10 100 0.4 0.4 - - 12 25 30 Unit V V V A A V V V V A A mA Power Down Supply Current REF = 0 MHz (Commercial) Document #: 38-07759 Rev. ** Page 3 of 11 PRELIMINARY 2.5V DC Electrical Specifications Parameter VDD VIL VIH IIL IIH VOL VOH IDD (PD mode) IDD Description Supply Voltage Input LOW Voltage Input HIGH Voltage Input Leakage Current Input HIGH Current Output LOW Voltage Output HIGH Voltage 0 Unit V V V A A V V V V A A mA VDD + 0.3 10 100 0.5 0.5 - - 12 25 45 Power Down Supply Current REF = 0 MHz (Commercial) 3.3V and 2.5V AC Electrical Specifications Parameter 1/t1 Description Maximum Frequency[7] (Input/Output) 3.3V High drive 3.3V Standard drive 2.5V High drive 2.5V Standard drive TIDC t2 / t1 t3,t4 Input Duty Cycle Output Duty Cycle[8] Rise, Fall Time (3.3V)[8] <133.3 MHz >133.3 MHz <133.3 MHz >133.3 MHz Std drive, CL = 30 pF, <100 MHz Std drive, CL = 22 pF, <133.3 MHz Std drive, CL = 15 pF, <167 MHz High drive, CL = 30 pF, <100 MHz High drive, CL = 22 pF, <133.3 MHz High drive, CL = 15 pF, >133.3 MHz t3, t4 Rise, Fall Time (2.5V)[8] Std drive, CL = 15 pF, <133.33 MHz High drive, CL = 30 pF, <100 MHz High drive, CL = 22 pF, <133.3 MHz High drive, CL = 15 pF, >133.3 MHz t5 t6 t7 Output to Output Skew [8] All outputs equally loaded Delay, REF Rising Edge to PLL enabled @ 3.3V CLKOUT Rising Edge[8] PLL enabled @2.5V Part to Part Skew [8] Test Conditions Min. 10 10 10 10 25 40 47 45 - - - - - - - - - - - -100 -200 - - Typ. - - - - - - - - - - - - - - - - - - 30 - - - - Max. 220 167 200 133 75 60 53 55 1.6 1.6 0.6 1.2 1.2 0.5 1.5 2.1 1.3 1.2 100 100 200 150 300 Unit MHz MHz MHz MHz % % % % ns ns ns ns ns ns ns ns ns ns ps ps ps ps ps Measured at VDD/2. Any output to any output, 3.3V supply Measured at VDD/2. Any output to any output, 2.5V supply Notes: 7. For the given maximum loading conditions. See CL in Operating Conditions Table 8. Parameter is guaranteed by design and characterization. Not 100% tested in production Document #: 38-07759 Rev. ** Page 4 of 11 PRELIMINARY 3.3V and 2.5V AC Electrical Specifications (continued) Parameter tLOCK TJCC[8,9] Description PLL Lock Time [8] CY23EP05 Min. - - - - - - - - - - - - - - Typ. - 22 45 45 40 35 52 18 13 28 26 25 22 19 Max. 1.0 55 125 100 100 80 125 60 35 75 70 60 60 45 Unit ms ps ps ps ps ps ps ps ps ps ps ps ps ps Test Conditions Stable power supply, valid clocks presented on REF and CLKOUT pins 3.3V supply, >66 MHz, <30 pF, standard drive 3.3V supply, >66 MHz, <30 pF, high drive 2.5V supply, >66 MHz, <15 pF, standard drive 2.5V supply, >66 MHz, <15 pF, high drive 2.5V supply, >66 MHz, <30 pF, high drive Cycle-to-cycle Jitter, Peak 3.3V supply, >66 MHz, <15 pF TPER [8,9] Period Jitter, Peak 3.3V supply, 66-100 MHz, <15 pF 3.3V supply, >100 MHz, <15 pF 3.3V supply, >66 MHz, <30 pF, standard drive 3.3V supply, >66 MHz, <30 pF, high drive 2.5V supply, >66 MHz, <15 pF, standard drive 2.5V supply, 66-100 MHz, <15 pF, high drive 2.5V supply, >100 MHz, <15 pF, high drive Switching Waveforms Duty Cycle Timing t1 t2 VDD/2 VDD/2 VDD/2 All Outputs Rise/Fall Time OUTPUT 2.0V(1.8V) 0.8V(0.6V) t3 2.0V(1.8V) 0.8V(0.6V) t4 3.3V(2.5V) 0V Output-Output Skew OUTPUT VDD/2 OUTPUT t5 VDD/2 Note: 9. As defined by JESD65B. Typical jitter is measured at 3.3V or 2.5V, 29C, with all outputs driven into the maximum specified load. Document #: 38-07759 Rev. ** Page 5 of 11 PRELIMINARY Switching Waveforms (continued) Input-Output Propagation Delay CY23EP05 INPUT VDD/2 FBK t6 VDD/2 Part-Part Skew Any output, Part 1 or 2 VDD/2 Any output, Part 1 or 2 t7 VDD/2 Test Circuits Test Circuit # 1 V DD 0.1 F CLK OUTPUTS C LOAD V DD 0.1 F GND GND Document #: 38-07759 Rev. ** Page 6 of 11 PRELIMINARY Supplemental Parametric Information CY23EP05 1000 800 600 400 200 0 -200 -400 -600 -800 -1000 -20 -10 0 10 20 Load CLKOUT- Load CLKn (pF) 2.5V Standard Drive 2.5V High Drive Figure 1. 2.5V typical room temperature graph for REF Input to CLKn delay versus loading difference between CLKOUT and CLKn. Data is shown for 66 MHz. Delay is a weak function of frequency. 1000 800 600 400 200 0 -200 -400 -600 -800 -1000 -20 -10 0 10 20 Load CLKOUT- Load CLKn (pF) Figure 2. 3.3V typical room temperature graph for REF Input to CLKn delay versus loading difference between CLKOUT and CLKn. Data is shown for 66 MHz. Delay is a weak function of frequency. 3.3V Standard Drive 3.3V High Drive Document #: 38-07759 Rev. ** Page 7 of 11 PRELIMINARY CY23EP05 70 60 50 40 30 20 10 0 33 66 100 133 Frequency (MHz) 15pF, -45C, Standard Drive 15pF, 90C, Standard Drive 15pF, -45C, High Drive 15pF, 90C, High Drive 30pF, -45C, High Drive 30pF, 90C, High Drive 166 200 Figure 3. 2.7V measured supply current versus frequency, drive strength, loading, and temperature. Note that the 30-pF data above 100 MHz is beyond the data sheet specification of 22 pF. 100 80 60 15pF, -45C, Standard Drive 15pF, 90C, Standard Drive 30pF, -45C, Standard Drive 30pF, 90C, Standard Drive 15pF, -45C, High Drive 15pF, 90C, High Drive 30pF, -45C, High Drive 30pF, 90C, High Drive 40 20 0 33 66 100 133 Frequency (MHz) 166 200 233 Figure 4. 3.6V measured supply current versus frequency, drive strength, loading, and temperature. Note that the 30-pF high-drive data above 100 MHz is beyond the data sheet specification of 22 pF. Document #: 38-07759 Rev. ** Page 8 of 11 PRELIMINARY 350 300 250 200 150 100 50 0 0 50 100 Frequency (MHz) 150 200 250 15 pF, Standard Drive 15 pF, High Drive 30 pF, Standard Drive 30 pF, High Drive CY23EP05 Figure 5. Typical 3.3V measured cycle-to-cycle jitter at 29C, versus frequency, drive strength, and loading 400 350 300 250 200 150 100 50 0 0 20 40 60 80 100 Frequency (MHz) 120 140 160 180 200 15 pF, Standard Drive 15 pF, High Drive 30 pF, High Drive Figure 6. Typical 2.5V measured cycle-to-cycle jitter at 29C, versus frequency, drive strength, and loading 250 15 pF, Standard Drive 15 pF, High Drive 30 pF, Standard Drive 30 pF, High Drive 200 150 100 50 0 0 50 100 Frequency (MHz) 150 200 250 Figure 7. Typical 3.3V measured period jitter at 29C, versus frequency, drive strength, and loading. 250 15 pF, Standard Drive 15 pF, High Drive 30 pF, High Drive 200 150 100 50 0 0 20 40 60 80 100 Frequency (MHz) 120 140 160 180 200 Figure 8. Typical 2.5V measured period jitter at 29C, versus frequency, drive strength, and loading Document #: 38-07759 Rev. ** Page 9 of 11 PRELIMINARY Ordering Information Ordering Code Lead-free CY23EP05SXC-1 CY23EP05SXC-T CY23EP05SXI-1 CY23EP05SXI-1T CY23EP05SXC-1H CY23EP05SXC-1HT CY23EP05SXI-1H CY23EP05SXI-1HT 8-pin 150-mil SOIC 8-pin 150-mil SOIC - Tape and Reel 8-pin 150-mil SOIC 8-pin 150-mil SOIC - Tape and Reel 8-pin 150-mil SOIC 8-pin 150-mil SOIC - Tape and Reel 8-pin 150-mil SOIC 8-pin 150-mil SOIC - Tape and Reel Package Type CY23EP05 Operating Range Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Package Drawing and Dimensions 8-lead 8 Lead (150 Mil) SOIC - S08 (150-Mil) SOIC S8 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 0.150[3.810] 0.157[3.987] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. SZ08.15 LEAD FREE PKG. 5 8 0.189[4.800] 0.196[4.978] SEATING PLANE 0.010[0.254] 0.016[0.406] X 45 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0~8 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 51-85066-*C All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07759 Rev. ** Page 10 of 11 (c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PRELIMINARY Document History Page Document Title: CY23EP05 2.5V or 3.3V, 10-220-MHz, Low Jitter, 5 Output Zero Delay Buffer Document Number: 38-07759 REV. ** ECN NO. 349620 Issue Date See ECN Orig. of Change RGL New data sheet Description of Change CY23EP05 Document #: 38-07759 Rev. ** Page 11 of 11 |
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